1. Technical Field
The inventive concept relates to a semiconductor memory device, and, more particularly, to a semiconductor memory device in which memories of different types are embedded.
2. Related Art
As the mobile and digital information communication and home appliance industries continue to develop, the demand for electron change control-based devices may reduce. Accordingly, a demand for new functional memory devices, other than the conventional electron charge devices, may increase. More specifically, development of next generation memory devices with high capacity, ultra-high speed, and low power is desired to meet the demand for high capacity memory of leading information devices.
Recently, embedded semiconductor devices in which multi-functional memory devices are integrated have been suggested. Such semiconductor devices are being developed to magnify mutual advantages of the memory devices and supplement mutual disadvantages of the memory devices.
Typically, the multi-functional semiconductor memory device is a semiconductor memory device in which a flash memory ‘A’ and a resistor element ‘B’ are combined as illustrated in FIG. 1. One flash memory and one resistor element are combined to constitute a memory cell of the semiconductor memory device.
Herein, the flash memory ‘A’ includes a stack gate structure formed on a semiconductor substrate 10 and a source 45a and a drain 45b formed in the semiconductor substrate 10 at both sides of the stack gate structure. The stack gate structure may be formed by stacking a tunneling insulating layer 15, a charge storage layer (or a charge trap layer) 20, a blocking layer 25, a control gate 30, and a hard mask layer 35. Insulating spacers 40 may be disposed on sidewalls of the stack gate structure.
The source 45a is electrically connected to a source interconnection 70 via a first contact plug 60 and the drain 45b is electrically connected to a bit line 75 via a second contact plug 65.
As well-known, the flash memory ‘A’ programs and erases charges in the charge storage layer 20 based on voltages applied to the control gate 30, the source interconnection 70, and the bit line 75.
Further, the resistor element ‘B’ is disposed on the stack gate structure of the flash memory ‘A’. The resistor element ‘B’ includes a resistor material 50, having a resistance that changes based on a voltage or current provided thereto, and a switch 55, selectively providing the current to the resistor material 50. The first and second contact plugs 60 and 65 are used as electrodes providing the current to the resistor material 50.
When the switch 55 is driven, the resistor element B stores data “0” or“1” based on a voltage difference between the first and second contact plugs 60 and 65.
However, the multi-functional semiconductor memory device has disadvantages because the resistor element ‘B’ is formed on the flash memory ‘A’.
The resistor element ‘B’ is disposed between the first and second contact plugs 60 and 65 and uses the first and second contact plugs 60 and 65 as electrodes. Because of this arrangement, materials that are optimal for use as electrodes for the resistor element B are not used. That is, materials used for the first and second contact plugs 60 and 65 are not optimal materials for use as electrodes for the resistor element B.
In addition, because the resistor element B is interposed between the first and second contact plugs 60 and 65, a width W1 of the resistor element B is not extended more than a line width W2 of a gate electrode (or a distance between the first and second contact plugs 60 and 65) so that there is limitation on varying a size of the resistor element B.
Moreover, the switch 55 is additionally required to drive the resistor element B and the switch 55 is also interposed in a space between the first and second contact plugs 60 and 65 so that the width W1 of the resistor element B is further reduced.
Furthermore, the reduced space makes fabricating the resistor element B and the switch 55 complicated.